1. Field of the Invention
The present invention relates in general to semiconductor technology. More particularly, it relates to a contact hole forming method for a semiconductor device.
2. Description of the Related Arts
One important technique for fabricating a semiconductor device involves forming a connection between an upper level wiring layer and either a conductive region of an impurity-diffused layer in a semiconductor substrate or a lower level wiring layer. Such a connection is preferably formed through a contact hole formed in interlayer insulating film.
As the density of integrated circuits has increased, the design rule, i.e., the minimum feature size, has decreased. With this increasing scale of integration of semiconductor devices, the diameters of contact holes are accordingly being made even smaller; however, it is difficult to reduce the depths of contact holes because of the need for wiring resistance or capacity. For this reason, the aspect ratios of contact holes have rapidly increased in recent years, and there has been a high demand for forming metal electrodes featuring good coverage.
FIGS. 1A to 1C are cross-sections at selected stages of a conventional fabrication process for forming a contact hole and a barrier metal film. Referring to FIG. 1A, on a semiconductor substrate 10, an interlayer dielectric (ILD) layer 14 is provided with a capping layer 12 interposed. The ILD layer 14 generally consists of one or more dielectric depositions of spin on glass (SOG), silicon oxide, borophosphosilicate (BPSG), and so on. The capping layer 12, serving as a diffusion barrier to prevent diffusion of impurities in the ILD layer 14 into the substrate 10, is typically silicon nitride (SiN), though other materials may be used.
Next, as illustrated in FIG. lB, a contact hole 16 is etched through the ILD layer 14 and the capping layer 12 using a photoresist pattern as a mask. The etching is further carried into the substrate 10 to a predetermined depth to form a recess portion 16a below the substrate surface. Here, because the silicon nitride capping layer 12 is less liable to be etched as compared with the substrate 10 and the ILD layer 14, an overhang configuration H is created within the contact hole 16 above the recess portion 16a. 
Thereafter, a conventional method of forming a contact is by sputtering a Ti/TiN barrier layer 18 over the ILD layer 14 and over bottom and sidewalls of the contact hole 16. However, as illustrated in FIG. 1C, the overhang H makes sputtering of the barrier layer very difficult. The step coverage of the Ti/TiN layer 18 is especially poor on sidewalls of the recess portion 16a. The insufficient coverage of Ti/TiN barrier 18 leads to high contact resistance and yield problems, and stable electrical characteristics of a contact electrode cannot be obtained. An improved method for forming a contact hole is thus desirable.
Therefore, an object of the invention to provide a method for forming a stepped contact hole that substantially obviates the above-mentioned problems.
To achieve the above and other objects, a method for forming a stepped contact hole is provided comprising the steps of: forming a capping layer on a substrate; sequentially forming a first dielectric layer and a second dielectric layer having different etch rates on the capping layer; etching a preliminary contact hole through the second dielectric layer, the first dielectric layer, the capping layer, and part of the way through the substrate; isotropically etching the sidewalls of the preliminary contact hole with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a contact hole having a stepped sidewall; and anisotropically etching to remove exposed portions of the capping layer.
In a preferred embodiment of the invention, the second dielectric layer is TEOS oxide, the first dielectric layer is BP-TEOS oxide, and the isotropic etching is carried out using a buffered HF solution.